Random access memory shift register system

ABSTRACT

A random access memory array wherein each storage cell includes an input, an output, a write control and a read control is coupled to a commutator system, the random access memory array is thereby operated by the commutator system to provide a shift register system. Various embodiments of the random access memory shift register system of the invention provide many advantages over conventional shift register systems including flexibility; high, low or variable speed; high density; and low power.

United States Patent 1191 Bell 2 July 1, 1975 RANDOM ACCESS MEMORY SHIFT 3,651,491 3/1972 Kabayashi 340/173 FF REGISTER SYSTEM 3,76l,898 9/l973 P30 340/l73 R [75] lnventor: Antony G. Bell, Houston, Tex. OTHER PUBLICATIONS [73] Assignee: Texas lnsmmems lncorpomed Anacker, Memory Employing Integrated Circuit Shift [)auas Register Rings, 6/68, IBM Technical Disclosure Bulletin, Vol. II, No. I, pp. l2-l3a. [221 1974 Beausoleil, Shift Register Storage, 10/70, IBM Techni- [21] Appl. No.: 460,259 cal Disclosure Bulletin, Vol. 13, No. 5, pp.

1336-1337. Related U.S. Application Data [63] Continuation of Ser. No. 163,682, July 19, 1971, Primary Examiner stuart Hacker abandoned Attorney, Agent, or Firm-Harold Levine; Edward J. 52 us. (:1. 340/173 R; 307/221 R John Graham [51] Int. Cl. Gllc 7/00; Gl lc 19/00 [58] Field of Search 307/238, 221 R, 221 B, 1 ABSTRACT 307/221 C; 340/ 7 173 l73 F, 173 A random access memory array wherein each storage RC cell includes an input, an out ut, a write control and a p read control is coupled to a commutator system, the [56] Relerences Cited random access memory array is thereby operated by UNITED STATES PATENTS the commutator system to provide a shift register sys- 2 823 368 2/1958 Avery 340 173 CA embodimems the random access 2:825:839 3/1958 Henlenm 34ol|73 CA memory shift register system of the invention provide 3,174,106 3/1965 Urba 307/22 R many advantages over conventional shift register sys- 3,3l3,926 4/l967 Minnickum 307/22! R terns including flexibility; high, low or variable speed; 3,504,353 3/1970 Guzak 307/238 X high density; and low power, 3,585,6l3 6/l97l Palfi 340/l73 R 0 3,588,847 6/1971 Dell 340/173 R 16 0mm, 17 Drawmg Flgures L2 L L 0 L A ac cu r r r r H10 lo lo io A1 81 c1 01 H W l T 1 r :r r r -m'- 1o'- 1o- -1n"' w A2 B2 C2 D2 R 3 r Y T r ID --1 l0 *4 in ID 1 A3 B3 C3 D3 W 1 1 1 L d r r r T A4 B4 C4 04 W 1 r 1 r W HTEHJUU SHEET 1 RANDOM ACCESS MEMORY SHIFT REGISTER SYSTEM This is a continuation of application Ser. No. 163,682, filed July 19, 197 I, now abandoned.

This invention relates to shift register systems and the like and, more particularly, to a shift register which utilizes a random access memory array or a portion thereof as a shift register system to store and shift coded information.

Many shift register systems for storing and shifting binary information are available. It is an object of this invention to provide a shift register system which is more flexible than conventional shift register systems. It is also an object of this invention to provide a highly stable electronic shift register system which is denser than conventional shift register systems to store and shift a greater number of bits of coded information in a given area. For example, in accordance with the present invention, an MOS (metal-insulatorsemiconductor) embodiment of the shift register system of the invention fabricated as an integrated semiconductor system requires approximately one-third of the area required by conventional MOS shift registers to store and shift an equal number of bits of binary information or can store and shift three times the number of bits of binary information which is stored and shifted in a conventional shift register of equal area. Another object of the invention is to provide a highly stable shift register which is independent of speed considerations. A further object of the invention is to provide an electronic shift register system which requires lower operating power than conventional shift registers. Still another object of the invention is to provide a unique logic and/or arithmetic system.

These and other objects are accomplished in accordance with the present invention by utilizing a random access memory array coupled to and operated in conjunction with a commutator system. The memory array is comprised of a plurality of memory cells capable of storing coded information, arranged in rows and colunins. Each memory cell includes input means for introducing coded information into the memory cell, output means for reading information out of the memory cell, write control means for addressing the memory cell in order to write coded information into the mem ory cell in order to read coded information out of the memory cell. Within each row of cells. the write control means are commoned and the read control means are commoned; within each column of cells, the input means are commoned and the output means are commoned. Furthermore, in one embodiment of the invention, the write control means of rows are commoned to the read control means of adjacent rows. In still another embodiment, the output means of columns are commoned with the input means of adjacent columns. The commutator system provides pulses to the write and read control means or to commoned write and read control means of rows of memory cells to sequentially operate rows of cells in the array and thereby provide a shift register system in accordance with the invention.

Still further objects and advantages of the invention will be apparent from the following detailed description and claims and from the accompanying drawings illustrative of various embodiments of the invention wherein:

FIGS. 1-8 are block diagrams illustrating various embodiments of the shift register system of the invention;

FIG. 9 is a circuit diagram illustrating an MOS or MIS embodiment of commutator 14;

FIGS. 10A12B are circuit diagrams and structure representations of MOS or MIS embodiment of memory cells 10 comprising memory array 13; and

FIG. 13 is a circuit diagram of an MOS or MIS embodiment of delay cells 12.

In accordance with the present invention a shift register system comprises a random access memory array. coupled to and operated in conjunction with a commutator system. The memory array is comprised of a plurality of memory cells capable of storing coded information, arranged in rows and columns. Each memory cell includes input means for introducing coded information into the memory cell, output means for reading information out of the memory cell, write control means for addressing the memory cell in order to write coded information into the memory cell, and read control means for addressing the memory cell in order to read coded information out of the memory cell. Within each row of cells, the write control means are commoned and the read control means are commoned; within each column of cells, the input means are commoned, and the output means are commoned. The commutator system sequentially distributes pulses to the write and read control means of rows to sequentially operate the rows of cells in the array and thereby provide the shift register system. In some embodiments of the invention, as is shown in the following detailed discussion of various embodiments of the shift register system, a unit of coded information such as a binary bit is stored in a cell and is not necessarily shifted through the memory array, but appears as a string of shifting coded information at the input and output lines of the shift register system.

Referring to FIG. 1, a first embodiment of the shift register system of the invention is shown which stores and shifts N series of bits :1 times. Thus, in this embodiment, 3 parallel input of a set of N bits is simultaneously introduced into the shift register at selected time periods and a parallel output of a set of N bits is simulta neously provided at the output of the shift register. The present invention shift register embodiment is comprised of random access memory array 13 having it rows (1, 2, 3, 4, 5, 6, 7, n) and N columns (A, B, C, ...N, where N represents the total number of columns and is not indicative of its numerical position in the alphabet) of random access memory cells. Each memory cell includes an input I, and output 0, a write control W, and a read control R. Within each row of cells (1, 2, 3, 4, 5, 6, 7, n), the write control means W are commoned and the read control means R are commoned. Thus, for example, cells A1, B1, C1, N1 have a common read line and a common write line. Within each column of cells (A, B, C, N), the input means I are commoned and the output means 0 are commoned. Thus, cells A1, A2, A3, A4, A5, A6, A7, An have a common input line IA and a common output line 0A.

The read and write lines (labeled R and W, respectively, because they are commoned with the read control means and write control means of the cells in the row) are coupled to a commutator 14. In this first embodiment, the commutator is comprised of a plurality of shift register cells 11 connected in series. Thus, the output of shift register cell IR is connected to the input of cell 1W, etc. The output of the last cell nW is coupled to the input ofthe first cell 1R. Thus. a pulse intro duced into the input of shift register cell IR is shifted to cell 1W, then from cell 1W to cell 2R, etc., and from cell nW to cell 1R so that it is recirculated through the shift register. Signals indicative of the state of each shift register cell is provided on output lines 15 so that at least one of the outputs 15 is indicative of the storage of a pluse in its respective shift register cell.

Various embodiments of random access memory cells 10 and shift register cells ll will later be described in detail. Consider in general, that when random access memory cells 10 are as stable or more stable than shift register cells, require a much smaller area than shift register cells and require much less power than shift register cells, the end result is a highly stable shift register system which is denser and requires less power than shift registers comprised solely of shift register cells. Where random access memory 13 of the shift register system has n rows of cells, n to 2:2 shift register cells are utilized in conjunction with memory array 13 to operate the shift register system. The number of columns of cells in the random access memory array is increased to any number without increasing the number of shift register cells required for operation of the system. and hence, the more random access memory cells utilized, the more advantageous the shift register system be comes.

The embodiment of FIG. 1 operates to read information from a cell to an output line and then write new in formation from the input line into the cell. Thus, when the output of shift register cell IR is indicative of the 5 pulse being stored in shift register cell lR information stored in memory cells Al, B1, C1, N] is read out from output lines OA. OB. OC, ON, respectively. When the output of shift register cell 1W is indicative ofthe pulse being stored in shift register cell 1W, information introduced into the memory array at inputs lA. lB. IC IN is stored in memory cells A], B1, C1, N]. respectively. Then when the output of shift register cell 2R is indicative of the pulse being stored in shift register cell 2R. information stored in memory cells A2, B2, C2, N2 is read out from output lines 0A, OB, OC, ON, respectively. When the output of shift register cell 2W is indicative of the pulse being stored in shift register cell 2W. information introduced into the memory array at inputs IA, IB, IC, IN, is stored in memory cells A2, B2, C2, N2, respectively, and so forth The operation of the shift register system of FIG. 1 over many time periods is shown in in TABLES l A-C. TABLES I A-C show the states of shift register cells ll, the state of memory cells 10, the information introduced at input lines IA, lB, IC, IN and the information provided at outputs OA. OB, 0C, ON for time periods 1 through 6N.

Bl hl bl bl (l cl cl cl NI dl dl dl d2 IA al :12

05 IB bl TABLE 1 CContinued A4 2112 1112 1112 alZ 1112 (112 a12 (1 A5 1113 a13 a13 n13 1113 1113 a13 2113 i113 A6 al4 (114 i114 a14 (114 L114 2114 (114 al4 A7 1115 4115 a15 a15 i115 1115 2115 (115 ul5 An 2116 :116 L116 alfi 1.116 alfi alfi i116 016 B1 199 U 1) O (J U U 0 B2 bli) blO blO 0 O (J U 0 0 B3 bll bll bll bll bll 0 O O (1 B4 1112 blZ blZ bl2 bl2 bl2 b12 O (1 B5 1113 bl bl3 1113 b13 bl3 bl b13 1113 B6 1314 b14 1114 M4 bl4 1314 i314 1114 1314 B7 1315 1115 M5 b15 b15 h15 b15 hi5 blS Bn hlfi b16 blo blfi 1116 blfi blo 1:16 blfi Cl c9 0 U U U 0 O U 0 C2 C10 C10 (:10 U 0 O U U (1 C3 cll cll C11 C11 C11 0 U U 0 C4 e12 C12 (:12 (:12 c12 e12 c12 11 0 C5 (13 C13 C13 C13 (:13 C13 C13 (:13 c1} C6 014 e14 C14 C14 e14 e14 e14 c14 (:14 (7 e15 e15 e15 C15 (15 (:15 e15 c15 c15 Cn C16 (:16 (:16 C16 e16 e16 clfi (:16 C16 N1 d9 0 l) (J O 0 0 U 0 N2 (1111 dlO dlO U 0 0 (1 0 0 N3 (111 (111 (111 (111 dll (1 0 0 N4 dlZ dl2 d12 c112 d12 dl2 dl2 [1 0 N5 dl3 (113 d13 dl3 (113 (113 (113 d13 (113 N6 d14 d14 d14 (114 (.114 d14 d14 d14 d14 N7 (115 dlS (115 dl5 d15 (115 dlS (115 (115 Nn dlfi dlfi (116 dlfi dlo (116 dl6 (116 dl6 1A (1 0 O 0 0A a9 alU all (112 (:13

IB (1 (1 O 0 08 b9 blO bll bl2 b13 1C 0 O (J 0 0C c9 C10 C11 c12 e13 IN 0 0 0 0 ON (19 dlO (111 (112 d13 (1 l) O 0 O (1 O 0 1) O O (1 (l 0 1114 .114 (I U U 0 0 a15 a15 a15 al5 (1 (l (l ulfi alt: alfi alfi (116 1116 U (1 U 1) O 11 0 U 0 11 (l 0 0 0 (l U U U U l) (J 0 U U U [l 0 Cl 0 U 0 0 0 0 U 0 M4 1314 0 0 O U 0 b15 b15 b15 b15 0 0 U b16 b16 blfi hlfi blfi M6 0 0 (J 0 U 0 O 0 U 0 (1 t1 1) 0 0 O 1] 11 ll (1 (J O U U U (1 0 U 0 11 U l) O 0 U (1 (:14 C14 0 t) O U 0 c15 (:15 C15 (:15 0 t) 0 (:16 e16 (:16 e16 clo e16 U 0 (J 0 0 (l 0 U 0 (1 U 0 t) (J (1 0 0 U 0 [1 (J 0 (I (l 0 U U 0 0 U U U 0 0 1.1 0 d14 d14 0 (1 O (1 U dlS dlS d15 (.115 (J U 0 dlfi 116 (116 dlfi d16 (116 O 0 0 U 0 2:14 1115 a16 ll 0 0 0 b14 b15 bio c14 clS (:16 0 U 0 U In the embodiment of P16. 1. the pulse first being introduced into shift register cell 1R provides an output from the memory cells of row 1 and then when the pulse is shifted to shift register cell 1W information is introduced into the first row of the memory array. thus providing a one time period delay before information is read into the shift register system. Shift register cells 11 of commutator 14 are rearranged in a second embodiment illustrated in FIG. 2, so that information is written into the system during the first time period. In order to accomplish this, the commutator imput pulse is first applied to shift register cell 1W and lastly to shift register cell 1R before recirculating the pulse the shift register cell 1W. The operation of this second embodiment of the shift register system for time period 1 through 6n is shown in TABLES Il AC.

Referring to FIG. 3, a third embodiment of the shift register system of the invention is shown which stores 3 and shifts N series of bits n times. Thus, similarly to the ONv In the third embodiment of the shift register system, again, within each row of memory cells 10, the write control means W are commoned and the read control means R are commoned; and, within each column of cells, the input means 1 are commoned and the output means 0 are commoned. Furthermore, in this third embodiment, the write control means W of the n th row is commoned to the read control means R of the 1st row and the write control means W of intermediate rows are commoned to the write control means W of the next adjacent rows as illustrated in FIG. 3.

TABLE 11 A 10 Al a1 a1 a1 a1 5 6 7 8 9 10 11 1213 14 r. 2nl Zn 211 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 at] TABLE II C IR 1 10 Al U U U U U U U U U U U U U U U U A2 alU alU U U U U 0 U U U U U U 0 U 0 A3 all all all all 0 0 U 0 U U U U U U U 0 A4 .112 2112 al2 n12 al2 al2 0 U U 0 U U U U U 0 A5 2113 2113 2113 2113 i113 al3 al3 al3 0 0 0 U U U 0 0 A6 al4 2114 2x14 1114 al4 1114 2114 al4 al4 al4 U U U U 0 U A7 al5 dl5 al5 alS al5 al5 al5 al5 M5 1115 alS al5 U U U U B1 0 U U U 0 O U U U U U U U U U U B2 b l O b 1 U U U U U U U U U U U U U U U B3 1111 bll bll bll U U U U U U U U U U U U B4 hl2 bl2 blZ hi2 hl2 hi2 U U U U U U U U U U B5 b1 bl3 bl3 hi3 hi3 [113 1313 bl] U U U U U 0 0 U Bo bl4 M4 M4 bl4 b14 bl4 hi4 hi4 [114 M4 0 U U U U 0 B7 hlS hlS M5 1115 1115 M5 M5 M5 M5 M5 M5 1315 U U U U Cl 0 O (l U U U U U U U U U (l O (l 0 C2 clU clU U U U U U U U U U U U U U 0 C3 cll Cll Cll CH O 0 U U U U U U (l (l (l 0 C4 012 cl2 e12 e12 e12 cl2 U U (1 U U U U U U 0 CS e13 (:13 C13 e13 e13 e13 c1 (:13 U U U U U U U U C6 C14 cl4 cl4 e14 (214 c14 e14 C14 C14 cl4 U U U U U U C7 C15 clS C15 cl5 C15 cl5 clS cl5 clS clS C15 C15 U U U U N1 0 U U U U U U U U U U U U U U U N2 dlO dlU U 0 U U U U U U U 0 U U U U N3 dll dll dll dll U 0 U U U U U U U U U U N4 d12 d12 d12 d12 d12 d12 0 U U 0 U U U U U U N5 c113 dl3 dl3 dl3 dl3 dl3 L113 (113 U U U U U U U U N6 dl4 dl4 dl4 dl4 dl4 dl4 dl4 dl4 dl4 dl4 U U U U U U [A 0 0 U U 0 U U 0 0A 2110 all a12 al3 al4 al5 alfi all 18 U U 0 U U 0 U U 08 blU bll bl2 hi3 hi4 blS blfi bU 1C 0 U 0 U U U U U 0C clO cll (:12 C13 e14 clS clfi c0 IN 0 0 U 0 U U U U ON dlU dll d12 d13 dl4 dl5 dlfi dU Thus, the write control line for row 1 is commoned with An. Bn, Cn,

the read control line of row 2, the write control line of row 2 is commoned with read control line of row 3, etc., and the write control line of the n-lth row (not shown) is commoned to the read control line of the n th row. For purposes of illustrating the commoning of the write and read control lines of adjacent rows of memory cells the individual write and read lines of adjacent rows are shown connected together. In a preferred embodiment, however, only a single common write/read line is provided in order to further reduce the size or increase the density of the shift register system. It should be noted that in this embodiment, because the read control means and the write control means of adjacent rows of cells are commoned only :1 shift register cells 11 are required to comprise the commutator sys tem 14. Thus, in the first time period information is written from inputs 1A 1B, 1C, 1N into memory cells Nn, respectively while simultaneously information stored in memory cells A], B1, C1, N1 is read out and provided at outputs 0A, OB, OC, ON. respectively. In the second time period new information is written into memory cells A1, B], C], N1 while simultaneously information is read out of memory cells A2, B2, C2, N2 and provided at outputs 0A. OB. 0C, ON, respectively. As long as information is read out of a row before new information is written into the row all information is preserved. The operation of the shift register system of FIG. 3 over many time periods is shown in TABLE III A and B. TABLES III A and B show the states of shift register cells II, the state of memory cells 10, the information introduced into input lines 1A, lB, 1C, IN and the information provided at outputs 0A, OB, OC, ON for time periods 1 through 3n.

TABLE III A TABLE III B -Continued OB b7 4.. b8 b) 1310 bit M2 M3 M4 M5 bl6 lC cl4 cl5 do 0 0 0 0 0 U 0 OC c7 c8 c9 010 CH cl2 cl3 cl4 cl5 clfi IN dl4 dl5 dl6 0 0 0 (l U 0 U ON d7 d8 d9 dlO dll dl2 dl3 dl4 dlS CH6 In the embodiment of FIG. 3, the pulse first being introduced into the lst shift register cell provides an output from the memory cells of row I and the storage of input information in row n. Thus, there is no time period delay before information is read into the shift register system. Shift register cells ll of commutator [4 may nevertheless be rearranged (similarly to FIG. 2) in a fourth embodiment illustrated in FIG. 4. so that information is written into the first row rather than the fourth row during the first time period. In order to accomplish this. the commutator input pulse is first applied to shift register cell 2 and lastly to shift register cell I before recirculating the pulse to shift register cell 2. The operation of this fourth embodiment of the shift register system for time periods I through 3n is shown in TABLES IV A and B.

Referring to FIG. 5, a fifth embodiment of the shift register system of the invention is shown which stores and shifts N X n bits of coded information. In this embodiment, a single series of bits is introduced into the input means I of column A during time periods 2 through N X n+1 and the series of bits is provided at output line 0 of the N th column during time periods (N X n)+l through 2N X n. Again. the shift register system is comprised of random access memory 13 having :1 rows (1, 2, 3. 4, 5. 6, 7, n) and N columns (A. B. C. N) of random access memory cells. The common input means I of column A provides means for inputting the coded information into the shift register system and the output means 0 of column N provides means for outputting the coded information from the shift register system. In addition. the output means of column A is coupled to the input means of column B by a storage or delay cell 12 (AB), the output means of column B is coupled to the input means of column C by a storage cell 12 (BC), etc.

TABLE IV A tl 2 3 4 5 6 7 n-l n n+1 n+2 n+3 n+4 n+5 n+6 l l 2 l 7 l l n l [0 AI al al al at al al al al al a9 a9 a9 a9 a9 219 A2 :12 a2 a2 a2 a2 a2 a2 a2 a2 altl all) all) alO alO A3 a3 a3 a3 a3 a3 a3 a3 a3 a3 all all all al I A4 a4 a4 a4 a4 a4 a4 a4 a4 a4 ul 2 al 2 al 2 A5 :15 a5 a5 a5 a5 a5 a5 a5 a5 s13 al 3 A6 a6 a6 a6 a6 a6 a6 a6 a6 a6 a l 4 A7 a7 a7 a7 a7 a7 a7 a7 a7 a7 An i all a8 a8 a8 a8 a8 a8 Bl bl bi bi bl bl bl bl bl bl b9 b9 b9 b9 b9 b9 B2 b2 b2 b2 b2 b2 b2 b2 b2 b2 hi0 bltl hlt) bit) M0 83 b3 b3 b3 b3 b3 b3 b3 b3 b3 bl l bll bl I bll 84 b4 b4 b4 b4 b4 b4 b4 b4 b4 M2 M2 M2 B5 b5 b5 b5 b5 b5 b5 b5 b5 b5 bl 3 bl 3 86 b6 b6 b6 b6 b6 b6 b6 b6 b6 M4 87 b7 b7 b7 b7 b7 b7 b7 b7 b7 Bn i b8 b8 b8 b8 b8 b8 b8 Cl cl cl cl cl cl cl cl cl cl (:9 c9 c9 c9 d9 C2 c2 c2 c2 c2 c2 c2 c2 c2 c2 CH1 CH1 cll) cl0 cit) C3 c3 c3 c3 c3 c3 c3 c3 c3 c3 cll cl 1 cl I cl l C4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c l 2 cl 2 cl 2 C5 c5 c5 c5 c5 c5 c5 c5 c5 c5 cl3 e13 C6 :6 c6 c6 c6 c6 c6 c6 c6 c6 c l 4 C7 c7 c7 c7 c7 c7 c7 c7 c7 :7 c8 c8 c8 c8 c8 c8 08 Nl dl dl dl dt dl d1 dl dt dl d9 d9 d9 d9 d9 d9 N2 d2 d2 d2 d2 d2 d2 d2 d2 d2 dlt) dlO dlO dlO dlU N3 d3 d3 d3 d3 d3 d3 d3 d3 d3 dl I dl I dll dll N4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d l 2 d l 2 d l 2 N5 d5 d5 d5 d5 d5 d5 d5 d5 d5 (3 dl3 N6 d6 d6 do do d6 d6 d6 d6 d6 d l 4 N7 d7 d7 d7 d7 d7 d7 d7 d7 d7 Nn i d8 d8 d8 d8 d8 d8 d8 IA al a2 a3 a4 a5 a6 a7 H. a8 :19 ul() all al2 al3 al4 0A d d) (b d) d it) d; al a2 a3 a4 a5 a6 a7 IB bl b2 b3 b4 b5 b6 b7 H. b8 b9 hlO bll M2 M3 M4 OB at d: 11; in da da dz bl b2 b3 b4 b5 ho b7 lC cl c2 c3 c4 c5 c6 c7 H. c8 c9 clt) cl] cl2 c|3 614 OC d 41 4: cl c2 c3 c4 c5 c6 c7 lN dl d2 d3 d4 d5 do d7 ii d8 d9 dlt) dll dl2 dl3 dld ON da da d d) (b d: d; d1 d2 d3 d4 d5 d6 d7 

1. A shift register system comprising: a. an array of random access memory cells arranged in rows and columns with the cells of a column having separate input and output lines common to all cells in a column; and b. commutator means effective to provide a continuous sequence of read/write signals coupled to said array for sequentially reading rows of said memory cells and simultaneously writing information into adjacent rows of memory cells via common read/write lines whereby coded information is stored in said array delayed by a selected number of time periods.
 2. The shift register system of claim 1 wherein each row of memory cells includes write address means for storing coded information into the row of memory cells and read address means for reading stored coded information out of said memory cells; and wherein the read address means of the first row is commoned with the write address means of the last row of said array and the read address means of intermediate rows are commoned with the write address means of adjacent rows.
 3. The shift register system of claim 1 wherein said commutator means is comprised of a plurality of series coupled shift register cells.
 4. The shift register system of claim 1, wherein the number of time periods of delay is equal to the number of series coupled shift register cells.
 5. The shift register system of claim 4 wherein the number of shift register cells is equal to the number of rows of memory cells in said memory array.
 6. A data memory system comprising: a. an array of random access memory cells arranged in rows and columns with the cells of a column having separate input and output lines common to all cells in a column; each cell having a read control input and a write control input; b. a plurality of address lines connected to the rows of cells wherein each address line within the array is connected in common to all of the read control inputs of all cells in a row and also connected to all of the write control inputs of all cells in an adjacent row; and c. address signal generator means producing a repeating sequence of separate addresses connected to the address lines for sequentially addressing the rows of cells, thereby sequentially reading rows of memory cells and simultaneously writing information into adjacent rows.
 7. A shift register system comprising: a. An array having a plurality of memory cells arranged in rows and columns, each row having write address means for storing coded information into the row of memory cells and read address means for reading stored coded information out of said memory cells; and b. commutator means selectively coupled to said write and read address means for distributing address signals to the read address means and then to the write address means of each row of cells in sequence whereby coded information is stored in said memory array and then read out of said memory array delayed by a selected number of time periods; wherein c. read address means of the first row of memory cells is commoned with the write address means of the last row of memory cells and the read address means of intermediate rows are commoned with the write address means of adjacent rows of said memory cells.
 8. The shift register system of claim 7 wherein the number of time periods of delay is equal to the number of rows of memory cells in the array.
 9. The shift register system of claim 7 wherein said commutator means is composed of a plurality of series coupled shift register cells, each shift register providing one time period of delay.
 10. The shift register system of claim 9 wherein one shift register cell is provided for each commoned/write address means to which such shift register cells are respectively coupled.
 11. A shift register system comprising: a. An array having a plurality of memory cells, each of said memory cells including: i. input means for introducing coded information into the memory cell, ii. output means for reading information out of the memory cells, iii. write control means for addressing the memory cell in order to store information in the memory cell, and iv. read control means for addressing the memory cell in order to read information out of the memory cell, said memory cells arranged in rows and columns, each having i. write address means coupled to each of the write control means of the cells in the respective row, and ii. read address means coupled to each of the read control means of the cells in the respective row, and each column having i. a column input means coupled to the input means of each memory cell in the respective column, and ii. a column output means coupled to the output means of each memory cell in the respective column; and b. commutator means coupled to the read and write address means of said rows of memory cells for selectively read and write addressing said rows of memory cells whereby information is stored in said memory array and is read out of said memory array delayed by a selected number of time periods, wherein c. the read address means of the first row of memory cells is commoned with the write address means of the last row of memory cells and the read address means of intermediate rows are commoned with the write address means of the adjacent rows of said memory cells.
 12. The shift register system of claim 11 including means commoning the column output means of the 1st to (n-1)th columns with the column input means of the 2nd to nth columns, respectively.
 13. The shift register system of claim 11 where in said commutator means is comprised of a plurality of series coupled shift register cells.
 14. The shift register system of claim 11 wherein said commutator means provides means for sequentially distributing address signals to the commoned read/write address means of each row of cells in sequence whereby coded information is stored in said memory array and then read out of said memory array delayed by a selected number of time periods.
 15. The shift register system of claim 14 wherein said commutator means is compries of a plurality of series coupled shift register cells, each shift register cell providing one time period of delay.
 16. The shift register system of claim 15 wherein one shift register cell is provided for each common read/write address means to which such shift register cells are respectively coupled. 